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Double Data Rate HBM3 Specification Introduced

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Double Data Rate HBM3 Specification Introduced
JEDEC has published the specification for a new version of the HBM DRAM standard, designated JESD238 HBM3. This memory will provide increased throughput compared to its predecessor HBM2 and increased speed of information processing in programs that require impressive power of the sublevel memory system.

The main parameters of the standard:
• Doubled transfer speed (up to 6.4 Gb/s per output, this equals 819 GB/s per device)
• The number of independent channels has been doubled to sixteen. Given that there are two pseudo-channels per channel, we can say that in fact HBM3 can implement thirty-two channels.
• Availability of 4-, 8-, 12-level TSV stacks, while in the future it will be possible to expand to 16 levels.
• Ensuring large density coverage of 8-32 Gb per layer, which will provide device capacity from 4 gigabytes (four layers of 8 Gb) to 64 gigabytes (sixteen - 32 Gb each). It is assumed that the new standard of the 1st generation will have layers of 16 Gbit.
• Ability to correct spontaneous ECC changes at the chip level.
• Improved power consumption through the use of low-swing (0.4 V) indicators and a reduced supply voltage of 1.1 V.

Documentation with the standard settings can be downloaded from the organization portal.
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